library ieee;
use ieee.std_logic_1164.all;

-- This arbitrary state machine is probably not very useful in reality, but demonstrates 

entity prbg is
    port (clock,reset         : in  std_logic;
          clock_en			  : in  std_logic;
          seed                : in  std_logic_vector(7 downto 0);
          load                : in  std_logic;
          prb                 : out std_logic_vector(7 downto 0)
    );
end prbg;

architecture behavior of prbg is

signal q                      : std_logic_vector(7 downto 0);
signal shiftin				  : std_logic;

component prbg_shift is
	port
	(
		aset		:in  std_logic;
		clock		:in  std_logic;
		data		:in  std_logic_vector(7 downto 0);
		enable		:in  std_logic;
		load		:in  std_logic;
		shiftin		:in  std_logic;
		q		    :out std_logic_vector(7 downto 0)
	);
end component;

begin

shift: prbg_shift port map(reset,clock,seed,clock_en,load,shiftin,q);

shiftin <= ((q(7) xor q(5)) xor q(4)) xor q(2);
prb <= q;

end behavior;